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? 1997 microchip technology inc. ds21224a-page 1 m 24lc08b/16b modules features iso 7816 compliant contact locations single supply with operation from 2.5-5.5v low power cmos technology - 1 ma active current typical - 10 m a standby current typical at 5.5v organized as 4 or 8 blocks of 256 bytes (4 x 256 x 8) or (8 x 256 x 8) 2-wire serial interface bus, i 2 c ? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz (2.5v) and 400khz (5v) compatibility self-timed write cycle (including auto-erase) page-write buffer for up to 16 bytes 2 ms typical write cycle time for page-write esd protection > 4,000v 1,000,000 erase/write cycles guaranteed data retention > 200 years temperature range description the microchip technology inc. 24lc08b/16b are 8k and 16k bit electrically erasable proms in iso mod- ules for smart card applications. the device is orga- nized as four or eight blocks of 256 x 8-bit memory with a 2-wire serial interface. the 24lc08b and 24LC16b also have a page-write capability for up to 16 bytes of data. iso module layout block diagram - commercial (c): 0?c to +70?c v ss sda scl v dd hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic sda scl v cc v ss 8k/16k i 2 c serial eeproms in iso micromodules i 2 c is a trademark of philips corporation.
24lc08b/16b modules ds21224a -page 2 ? 1997 microchip technology inc. 1.0 electrical chara cteristics 1.1 maxim um ratings* v cc ................................................................................... 7.0v all inputs and outputs w .r .t. v ss ................ -0.6v to v cc +1.0v stor age temper ature ..................................... -65?c to +150?c ambient temp . with po w er applied ................. -65?c to +125?c solder ing temper ature of leads (10 seconds) ............. +300?c esd protection on all pins .................................................. 3 4 kv *notice: stresses abo v e those listed under ?axim um r atings ma y cause per manent damage to the de vice . this is a stress r at- ing only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . t able 1- 1: pin function tab le name function v ss ground sd a ser ial data scl ser ial cloc k v cc +2.5v to 5.5v p o w er supply t able 1-2 dc c haracteristics all p ar ameters apply across the speci- ed oper ating r anges unless otherwise noted. commercial (c): t amb = 0?c to +70?c , v cc = 2.5v to 5.5v p arameter symbol min. max. units conditions scl and sd a pins: high le v el input v oltage v ih 0.7 v cc v (note) lo w le v el input v oltage v il 0.3 v cc v (note) hysteresis of schmitt tr igger inputs v hys 0.05 v cc v vcc 3 2.5v (note) lo w le v el output v oltage v ol 0.40 v i ol = 3.0 ma, v cc = 4.5v i ol = 2.1 ma, v cc = 2.5v input leakage current i li -10 10 m a v in = v cc or v ss output leakage current i lo -10 10 m a v out = v cc or v ss pin capacitance (all inputs/outputs) c in , c out 10 pf v cc = 5.0v (note) t amb = 25?c , f = 1 mhz oper ating current i cc wr ite 3 ma v cc = 5.5v , scl = 400 khz i cc read 1 ma v cc = 5.5v , scl = 400 khz standb y current i ccs 100 m a v cc = 5.5v , sd a = scl = v cc note: this par ameter is per iodically sampled and not 100% tested.
24lc08b/16b modules ? 1997 microchip technology inc. ds21224a -page 3 t able 1-3 a c c haracteristics figure 1-1: bus timing data all par ameters apply across the speci ed oper at- ing r anges unless otherwise noted. vcc = 2.5v to 5.5v commercial (c): t amb = 0 c to +70 c p arameter symbol vcc = 2.5v - 5.5v std mode vcc = 4.5v - 5.5v f ast mode units remarks min. max. min. max. cloc k frequency f clk 100 400 khz cloc k high time t high 4000 600 ns cloc k lo w time t low 4700 1300 ns sd a and scl r ise time t r 1000 300 ns ( note 1 ) sd a and scl f all time t f 300 300 ns ( note 1 ) st ar t condition hold time t hd : sta 4000 600 ns after this per iod the rst cloc k pulse is gener ated st ar t condition setup time t su : sta 4700 600 ns only rele v ant f or repeated st ar t condition data input hold time t hd : dat 0 0 ns ( note 2 ) data input setup time t su : dat 250 100 ns st op condition setup time t su : sto 4000 600 ns output v alid from cloc k t aa 3500 900 ns ( note 2 ) bus free time t buf 4700 1300 ns time the b us m ust be free bef ore a ne w tr ansmission can star t output f all time from v ih minim um to v il maxim um t of 250 20 +0.1 c b 250 ns (note 1), c b 100 pf input lter spik e suppression (sd a and scl pins) t sp 50 50 ns ( notes 1, 3) wr ite cycle time t wc 10 10 ms byte or p age mode endur ance 1m 1m cycles 25 c , v cc = 5.0v , bloc k mode ( note 4 ) note 1: not 100% tested. c b = total capacitance of one b us line in pf . 2: as a tr ansmitter , the de vice m ust pro vide an inter nal minim um dela y time to br idge the unde ned region (minim um 300 ns) of the f alling edge of scl to a v oid unintended gener ation of st ar t or st op conditions . 3: the combined t sp and v hys speci cations are due to schmitt tr igger inputs which pro vide impro v ed noise spik e suppression. this eliminates the need f or a ti speci cation f or standard oper ation. 4: this par ameter is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c application, please consult the t otal endur ance model which can be obtained on our bbs or w ebsite . t su : sta t f t low t high t r t hd : dat t su : dat t su : sto t hd : sta t buf t aa t aa t sp t hd : sta scl sd a in sd a out
24lc08b/16b modules ds21224a -page 4 ? 1997 microchip technology inc. 2.0 p ad descriptions 2.1 sd a (serial data) this is a bi-directional pin used to tr ansf er addresses and data into and data out of the de vice . it is an open dr ain ter minal, theref ore the sd a b us requires a pull-up resistor to v cc (typical 10 w ). f or nor mal data tr ansf er sd a is allo w ed to change only dur ing scl lo w . changes dur ing scl high are reser v ed f or indicating the st ar t and st op condi- tions . 2.2 scl (serial cloc k) this input is used to synchroniz e the data tr ansf er from and to the de vice . 3.0 functional description the 24lc08b/16b suppor ts a bi-directional 2-wire b us and data tr ansmission protocol. a de vice that sends data onto the b us is de ned as tr ansmitter , and a de vice receiving data as receiv er . the b us has to be controlled b y a master de vice which gener ates the ser ial cloc k (scl), controls the b us access , and gener- ates the st ar t and st op conditions , while the 24lc08b/16b w or ks as sla v e . both, master and sla v e can oper ate as tr ansmitter or receiv er b ut the master de vice deter mines which mode is activ ated. 4.0 b us chara cteristics the f ollo wing b us pr otocol has been de ned: data tr ansf er ma y be initiated only when the b us is not b usy . dur ing data tr ansf er , the data line m ust remain stab le whene v er the cloc k line is high. changes in the data line while the cloc k line is high will be inter preted as a st ar t or st op condition. accordingly , the f ollo wing b us conditions ha v e been de ned ( figure 5-2 ). 4.1 bus not busy (a) both data and cloc k lines remain high. 4.2 star t data t ransf er (b) a high to lo w tr ansition of the sd a line while the cloc k (scl) is high deter mines a st ar t condition. all commands m ust be preceded b y a st ar t condi- tion. 4.3 stop data t ransf er (c) a lo w to high tr ansition of the sd a line while the cloc k (scl) is high deter mines a st op condition. all oper ations m ust be ended with a st op condition. 4.4 data v alid (d) the state of the data line represents v alid data when, after a st ar t condition, the data line is stab le f or the dur ation of the high per iod of the cloc k signal. the data on the line m ust be changed dur ing the lo w per iod of the cloc k signal. there is one cloc k pulse per bit of data. each data tr ansf er is initiated with a st ar t condition and ter minated with a st op condition. the n umber of the data b ytes tr ansf erred betw een the st ar t and st op conditions is deter mined b y the master de vice and is theoretically unlimited, although only the last 16 will be stored when doing a wr ite oper ation. when an o v erwr ite does occur it will replace data in a rst in rst out f ashion.
24lc08b/16b modules ? 1997 microchip technology inc. ds21224a -page 5 4.5 ac kno wledg e each receiving de vice , when addressed, is ob liged to gener ate an ac kno wledge after the reception of each b yte . the master de vice m ust gener ate an e xtr a cloc k pulse which is associated with this ac kno wledge bit. the de vice that ac kno wledges , has to pull do wn the sd a line dur ing the ac kno wledge cloc k pulse in such a w a y that the sd a line is stab le lo w dur ing the high per iod of the ac kno wledge related cloc k pulse . of course , setup and hold times m ust be tak en into account. dur ing reads , a master m ust signal an end of data to the sla v e b y no t gener ating an ac kno wledge bit on the last b yte that has been cloc k ed out of the sla v e . in this case , the sla v e ( 24lc08b/16b ) will lea v e the data line high to enab le the master to gener ate the st op condition. 5.0 de vice ad dressing a control b yte is the rst b yte receiv ed f ollo wing the star t condition from the master de vice . the control b yte consists of a 4-bit control code , f or the 24lc08b/16b this is set as 1010 binar y f or read and wr ite oper ations . the ne xt three bits of the control b yte are the b loc k select bits (b2, b1, b0). the y are used b y the master de vice to select which of the eight 256 w ord b loc ks of memor y are to be accessed. these bits are in eff ect the three most signi cant bits of the w ord address . the last bit of the control b yte de nes the oper ation to be perf or med. when set to one a read oper ation is selected, when set to z ero a wr ite oper ation is selected. f ollo wing the star t condition, the 24lc08b/16b moni- tors the sd a b us chec king the de vice type identi er being tr ansmitted, upon a 1010 code the sla v e de vice outputs an ac kno wledge signal on the sd a line . depending on the state of the r/ w bit, the 24lc08b/ 16b will select a read or wr ite oper ation. figure 5-1: contr ol b yte allocation figure 5-2: d a t a transfer seq uence on the serial b us note: the 24lc08b/16b does not gener ate an y ac kno wledge bits if an inter nal prog r am- ming cycle is in prog ress . operation contr ol code bloc k select r/ w read 1010 bloc k address 1 wr ite 1010 bloc k address 0 sla ve address 1 0 1 0 b2 b1 b0 r/w a st ar t read/ write (a) (b) (d) (d) (a) (c) st ar t condition address or a ckno wledge v alid d a t a allo wed t o change st op condition scl sd a
24lc08b/16b modules ds21224a -page 6 ? 1997 microchip technology inc. 6.0 write opera tions 6.1 byte write f ollo wing the star t condition from the master , the de vice code (4 bits), the b loc k address (3 bits), and the r/ w bit which is a logic lo w is placed onto the b us b y the master tr ansmitter . this indicates to the addressed sla v e receiv er that a b yte with a w ord address will f ollo w after it has gener ated an ac kno wledge bit dur ing the ninth cloc k cycle . theref ore the ne xt b yte tr ansmitted b y the master is the w ord address and will be wr itten into the address pointer of the 24lc08b/16b . after receiv- ing another ac kno wledge signal from the 24lc08b/16b the master de vice will tr ansmit the data w ord to be wr it- ten into the addressed memor y location. the 24lc08b/ 16b ac kno wledges again and the master gener ates a stop condition. this initiates the inter nal wr ite cycle , and dur ing this time the 24lc08b/16b will not gener ate ac kno wledge signals ( figure 6-1 ). 6.2 p a g e write the wr ite control b yte , w ord address and the rst data b yte are tr ansmitted to the 24lc08b/16b in the same w a y as in a b yte wr ite . but instead of gener ating a stop condition the master tr ansmits up to 16 data b ytes to the 24lc08b/16b which are tempor ar ily stored in the on-chip page b uff er and will be wr itten into the memor y after the master has tr ansmitted a stop condition. after the receipt of each w ord, the f our lo w er order address pointer bits are inter nally incremented b y one . the higher order se v en bits of the w ord address remains constant. if the master should tr ansmit more than 16 w ords pr ior to gener ating the stop condition, the address counter will roll o v er and the pre viously receiv ed data will be o v erwr itten. as with the b yte wr ite oper ation, once the stop condition is receiv ed an inter- nal wr ite cycle will begin ( figure 6-2 ). figure 6-1: byte write figure 6-2: pa g e write s p b us a ctivity master sd a line b us a ctivity s t a r t s t o p contr ol byte w ord address d a t a a c k a c k a c k s p b us a ctivity master sd a line b us a ctivity s t a r t contr ol byte w ord address (n) d a t a n d a t a n + 15 s t o p a c k a c k a c k a c k a c k d a t a n + 1
24lc08b/16b modules ? 1997 microchip technology inc. ds21224a -page 7 7.0 a ckno wledge polling since the de vice will not ac kno wledge dur ing a wr ite cycle , this can be used to deter mine when the cycle is complete (this f eature can be used to maximiz e b us throughput). once the stop condition f or a wr ite com- mand has been issued from the master , the de vice ini- tiates the inter nally timed wr ite cycle . a ck polling can be initiated immediately . this in v olv es the master send- ing a star t condition f ollo w ed b y the control b yte f or a wr ite command (r/ w = 0). if the de vice is still b usy with the wr ite cycle , then no a ck will be retur ned. if the cycle is complete , then the de vice will retur n the a ck and the master can then proceed with the ne xt read or wr ite command. see figure 7-1 f or o w diag r am. figure 7-1: ac kno wledg e polling flo w 8.0 read opera tions read oper ations are initiated in the same w a y as wr ite oper ations with the e xception that the r/ w bit of the sla v e address is set to one . there are three basic types of read oper ations: current address read, r andom read, and sequential read. 8.1 current ad dress read the 24lc08b/16b contains an address counter that maintains the address of the last w ord accessed, inter- nally incremented b y one . theref ore , if the pre vious access (either a read or wr ite oper ation) w as to address n, the ne xt current address read oper ation w ould access data from address n + 1. upon receipt of the sla v e address with r/ w bit set to one , the 24lc08b/16b issues an ac kno wledge and tr ansmits the 8-bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the 24lc08b/16b discontin ues tr ansmission ( figure 8-1 ). 8.2 random read random read oper ations allo w the master to access an y memor y location in a r andom manner . t o perf or m this type of read oper ation, rst the w ord address m ust be set. this is done b y sending the w ord address to the 24lc08b/16b as par t of a wr ite oper ation. after the w ord address is sent, the master gener ates a star t con- dition f ollo wing the ac kno wledge . this ter minates the wr ite oper ation, b ut not bef ore the inter nal address pointer is set. then the master issues the control b yte again b ut with the r/ w bit set to a one . the 24lc08b/ 16b will then issue an ac kno wledge and tr ansmits the 8-bit data w ord. the master will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the 24lc08b/16b discontin ues tr ansmission ( figure 8-2 ). 8.3 sequential read sequential reads are initiated in the same w a y as a r an- dom read e xcept that after the 24lc08b/16b tr ansmits the rst data b yte , the master issues an ac kno wledge as opposed to a stop condition in a r andom read. this directs the 24lc08b/16b to tr ansmit the ne xt sequen- tially addressed 8 bit w ord ( figure 8-3 ). t o pro vide sequential reads the 24lc08b/16b contains an inter nal address pointer which is incremented b y one at the completion of each oper ation. this address pointer allo ws the entire memor y contents to be ser ially read dur ing one oper ation. 8.4 noise pr otection the 24lc08b/16b emplo ys a v cc threshold detector circuit which disab les the inter nal er ase/wr ite logic if the v cc is belo w 1.5 v olts at nominal conditions . the scl and sd a inputs ha v e schmitt tr igger and lter circuits which suppress noise spik es to assure proper de vice oper ation e v en on a noisy b us . send wr ite command send stop condition to initiate wr ite cycle send star t send control byte with r/w = 0 did de vice ac kno wledge (a ck = 0)? ne xt oper ation no yes
24lc08b/16b modules ds21224a -page 8 ? 1997 microchip technology inc. figure 8-1: current ad dress read figure 8-2: random read figure 8-3: sequential read s p b us a ctivity master sd a line b us a ctivity s t a r t s t o p contr ol byte d a t a n a c k n o a c k s p s b us a ctivity master sd a line b us a ctivity s t a r t s t o p contr ol byte a c k w ord address (n) contr ol byte s t a r t d a t a (n) a c k a c k n o a c k p b us a ctivity master sd a line b us a ctivity s t o p contr ol byte a c k n o a c k d a t a n d a t a n + 1 d a t a n + 2 d a t a n + x a c k a c k a c k
24lc08b/16b modules ? 1997 microchip technology inc. ds21224a -page 9 9.0 shipping method the micromodules will be shipped to customers in clear plastic tr a ys . each tr a y holds 150 modules , and the tr a ys can be stac k ed in a manner similar to shipping die in w af e pac ks . a tr a y dr a wing with dimensions is sho wn in figure 9-1 . figure 9-1: t ra y dimensions smart card modules 14.000 [355.60] 12.040 [305.82] 9.374 [238.09] 0.500 [12.70] 0.980 [24.89] typ 0.860 [21.84] typ. 0.617 [15.68] 0.905 [22.99] r 0.300 [7.62] typ r 0.270 [6.86] typ 8.145 [206.88] antistatic
24lc08b/16b modules ds21224a -page 10 ? 1997 microchip technology inc. figure 9-2: module dimensions 0.465 0.002 [11.80 0.05] 0.419 0.002 [10.63 0.05] a a 0.270 [6.86] max. 0.232 0.002 [5.90 0.05] r. 0.059 [1.50] (4x) 0.090 [2.29] min epoxy free area (typ.) 0.1043 0.002 [2.65 0.05] (8x) 0.146 0.002 [3.71 0.05] 0.174 0.002 [4.42 0.05] 0.209 0.002 [5.31 0.05] typ. device side contact side 0.1043 0.002 [2.65 0.05] 0.285 [7.24] max via holes (8x) i.d. ? 0.026 [0.66] o.d. ? 0.042 [1.06] gold flash 3-7 0.004 [0.10] max. copper base nickel plated, 150 min glob size 0.007 [0.18] max. section a-a fr4 tape die m in m in 0.015 [0.38] max. 0.0235 [0.60] max.
24lc08b/16b modules ? 1997 microchip technology inc. ds21224a -page 11 24lc08b/16b modules pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: mt = micromodules in tr a ys t emperature rang e: blank = 0 ? c to +70 ? c de vice: 24lc08b 8k bit 2.5v i 2 c ser ial eepr om in iso module 24LC16b 16k bit 2.5v i 2 c ser ial eepr om in iso module 24lc08b/16b ? /mt data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required). please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life sup port systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the m icrochip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21224a-page 12 ? 1997 microchip technology inc. m all rights reserved. ? 1997, microchip technology incorporated, usa. 9/97 printed on recycled paper. americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-4036 fax: 91-80-559-9840 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 singapore microchip technology taiwan singapore branch 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2-717-7175 fax: 886-2-545-0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44-1628-851077 fax: 44-1628-850259 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 8/29/97 w orldwide s ales & s ervice

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